From Fedora Project Wiki

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Icarus Verilog or '''iverilog''' is a Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard.  
 
Icarus Verilog or '''iverilog''' is a Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard.  
  
In Fedora 15 '''iverilog''' has been built against version 0,9.3. As declared in upstream, within the v0.9 series major changes are kept to a minimum, allowing some new features only if they do not risk the stability of the branch or of Verilog programs that use this compiler. Some changes of this release are related to ''Language Coverage'' with remotion of obsolete VAMS $log function, addition of a warning that synthesis is not currently being maintained when -S is used; named blocks now keep their scope information and it has been added the correct version information to the data structure returned by the PLI vpi_get_vlog_info() call. Regarding the ''Language Extensions''  it has been added FST dumper, +timescale to the command file; ability to automatically perform bit <-> real conversion for module inputs/outputs where this makes sense; optional warnings for out of range bit/part selects; and $info(), $warning() and $error() as aliases for $display.
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In Fedora 15 '''iverilog''' has been built against version 0,9.3. As declared in upstream, within the v0.9 series major changes are kept to a minimum, allowing some new features only if they do not risk the stability of the branch or of Verilog programs that use this compiler. Some changes of this release are related to ''Language Coverage'' with remotion of obsolete VAMS $log function; addition of a warning that synthesis is not currently being maintained when -S is used; named blocks now keep their scope information; and it has been added the correct version information to the data structure returned by the PLI vpi_get_vlog_info() call. Regarding the ''Language Extensions''  it has been added FST dumper; +timescale to the command file; ability to automatically perform bit <-> real conversion for module inputs/outputs where this makes sense; optional warnings for out of range bit/part selects; and $info(), $warning() and $error() as aliases for $display.  
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For a complete list of these features, with the general bug fixes and some of the things that still don't work, please refer to:
  
 
http://www.icarus.com/eda/verilog/index.html
 
http://www.icarus.com/eda/verilog/index.html
 
  
 
=== ngspice ===
 
=== ngspice ===

Revision as of 14:20, 23 March 2011

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Circuit Design

This section includes the set of applications for schematic capture, circuit simulation and PCB layout that have had major changes with Fedora 15.


gtkwave

gtkwave is an analysis tool used to perform debugging on Verilog or VHDL simulation models.

With Fedora 15 gtkwave has been upgraded to 3.3.20, with improvements and new features respect to the release 3.3.10 present in Fedora 14. Among these there are: additions of new tcl functions to enhance Tcl access; added support for process and transaction filters in MinGW and support for Open New Window to MinGW; in order to aid in indexing, detection for Verilog XL-style VCD identifiers in all vcd loaders in gtkwave. Updates to manual supporting GTKWave 3.3.20. For all details and fixes, refer to the CHANGELOG.TXT in the package doc directory.

http://gtkwave.sourceforge.net/

iverolg

Icarus Verilog or iverilog is a Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard.

In Fedora 15 iverilog has been built against version 0,9.3. As declared in upstream, within the v0.9 series major changes are kept to a minimum, allowing some new features only if they do not risk the stability of the branch or of Verilog programs that use this compiler. Some changes of this release are related to Language Coverage with remotion of obsolete VAMS $log function; addition of a warning that synthesis is not currently being maintained when -S is used; named blocks now keep their scope information; and it has been added the correct version information to the data structure returned by the PLI vpi_get_vlog_info() call. Regarding the Language Extensions it has been added FST dumper; +timescale to the command file; ability to automatically perform bit <-> real conversion for module inputs/outputs where this makes sense; optional warnings for out of range bit/part selects; and $info(), $warning() and $error() as aliases for $display.

For a complete list of these features, with the general bug fixes and some of the things that still don't work, please refer to:

http://www.icarus.com/eda/verilog/index.html

ngspice

ngspice is a general-purpose circuit simulator program. It implements three classes of analysis: Nonlinear DC analyses, Nonlinear Transient analyses and Linear AC analyses.

With F15, ngspice has been upgraded to release 22. In this update, more features have been added to ngspice, improving its compatibility through an extensive code cleanup that considerably reduces compiler warnings; improving its speed with the availabilty of OpenMP multicore support for BSIM3, BSIM4, and BSIMSOI4 that speeds up transistor loaded simulation by a factor of two; and improving its stability. In particular, the new feauture include: reinstate expansion in interactive interpreter; .TITLE line added; update to 'spectrum' script; par('expression') in .four, .plot, .print, .meas, .save commands; command 'option' for use in spinit, .spiceinit and in scripts; adms procedure updated; new random number generator, new random functions sunif() and sgauss(), and scripts for Monte Carlo simulations, new plot vectors allv, alli, ally. Manuals and documents follow the updates.

http://ngspice.sourceforge.net


pcb

An interactive printed circuit board editor.

In F15, pcb has been upgraded to release 20100929, with many bug fixes and new features. Among these are to cite: direct importing of schematics during runtime; places accept measurements' unit; the polygon hole tool; DBUS enabled by default (when possible); action scripts run by the CLI exporters; no more required the (,,) syntax of CLI actions in GUI; and tool-tips pop-up on elements, pins and nets; new GCode exporter and updated reference card.

http://pcb.sourceforge.net


rcrpanel

rcrpanel is a command line application that takes a text description of a panel and produces a PostScript rendering of the panel. It is especially handy for things like calibrated dial faces that can be tedious to produce with a traditional graphics application. rcrpanel is described in detail in the Fedora Amateur Radio Guide.