|
|
| (36 intermediate revisions by 4 users not shown) |
| Line 1: |
Line 1: |
| {{header|docs}} | | {{header|docs}}{{Docs_beat_closed}} |
| {{Docs_beat_open}} | |
| {{Draft}}
| |
| | |
| = Circuit Design =
| |
| This section includes the set of applications for schematic capture, circuit simulation and PCB layout that have had major changes with Fedora 15.
| |
| | |
| === archimedes ===
| |
| Rebuild for F15 against GNU Archimedes release 0.9.1: no up-stream changes
| |
| | |
| http://www.gnu.org/software/archimedes/
| |
| | |
| | |
| === drawtiming ===
| |
| Rebuild for F15 against drawtiming release 0.7.1: no up-stream changes
| |
| | |
| http://drawtiming.sourceforge.net
| |
| | |
| | |
| | |
| === gtkwave ===
| |
| '''gtkwave''' is an analysis tool used to perform debugging on Verilog or VHDL simulation models.
| |
| | |
| With Fedora 15 '''gtkwave''' has been upgraded to 3.3.18, with improvements and new features respect to the release 3.3.10 present in Fedora 14. Among these there are:
| |
| additions of new tcl functions to enhance Tcl access; added support for process and transaction filters in MinGW and support for Open New Window to MinGW; in order to aid in indexing, detection for Verilog XL-style VCD identifiers in all vcd loaders in gtkwave. Updates to manual supporting GTKWave 3.3.18. For all details and fixes, view the CHANGELOG.TXT in the doc package.
| |
| | |
| http://gtkwave.sourceforge.net/
| |
| | |
| | |
| | |
| === kicad ===
| |
| (At now rebuilded against 2010.05.27-2363)
| |
| | |
| ??
| |
| | |
| '''kicad''' is a set of applications used to capture electronic schematics and design printed circuit boards.
| |
| | |
| With Fedora 15, '''kicad''' has been upgraded from 2010.05.27 to 2011.mm.dd. Among the new features: addition of a tool (bitmap2component) to create logos from .bmp bitmaps, vectored by potrace for no pixelation effect. In eeschema: addition of "template fieldnames"; netlist generation, changes the rule to calculate netnames of nets with labels; exporting of the generic netlist in XML. In gerbview: improved support to Gerber language; added in file dialog, multiple file selection; Draw mode selector (in left toolbar). For all details, view the [http://bazaar.launchpad.net/~kicad-testing-committers/kicad/testing/annotate/head%3A/CHANGELOG.txt CHANGELOG.TXT (rev.2794)].
| |
| | |
| https://launchpad.net/kicad
| |
| | |
| ??
| |
| | |
| === mot-adms ===
| |
| Rebuild for F15 against adms-2.2.8: no up-stream changes
| |
| | |
| http://mot-adms.sourceforge.net/
| |
| | |
| | |
|
| |
| === ngspice ===
| |
| '''ngspice''' is a general-purpose circuit simulator program. It implements three classes of analysis: Nonlinear DC analyses, Nonlinear Transient analyses and Linear AC analyses.
| |
| | |
| With F15, '''ngspice''' has been upgraded to release 22. In this update, more features have been added to '''ngspice''', improving its compatibility through an extensive code cleanup that considerably reduces compiler warnings; improving its speed with the availabilty of OpenMP multicore support for BSIM3, BSIM4, and BSIMSOI4 that speeds up transistor loaded simulation by a factor of two; and improving its stability. In particular, the new feauture include: reinstate expansion in interactive interpreter; .TITLE line added; update to 'spectrum' script; par('expression') in .four, .plot, .print, .meas, .save commands; command 'option' for use in spinit, .spiceinit and in scripts; adms procedure updated; new random number generator, new random functions sunif() and sgauss(), and scripts for Monte Carlo simulations, new plot vectors allv, alli, ally. Manuals and documents follow the updates.
| |
| | |
| http://ngspice.sourceforge.net
| |
| | |
| (tclspice-22-5.cvs20101113.fc15.i686)
| |
| | |
| | |
| | |
| === pcb ===
| |
| http://pcb.sourceforge.net
| |
| | |
| | |
| | |
| === perl-Verilog ===
| |
| http://www.veripool.org/wiki/verilog-perl
| |
| | |
| perl-Hardware-Verilog-Parser-0.13-6.fc15.noarch
| |
|
| |
| perl-Hardware-Vhdl-Lexer-1.00-7.fc15.noarch
| |
| | |
| perl-Hardware-Vhdl-Parser-0.12-7.fc15.noarch
| |
| | |
| perl-Hardware-Vhdl-Tidy-0.8-8.fc15.noarch
| |
| | |
| perl-ModelSim-List-0.06-6.fc15.noarch
| |
| | |
| perl-Perlilog-0.3-6.fc15.noarch
| |
| | |
| perl-SystemC-Vregs-1.463-5.fc15.noarch
| |
| | |
| perl-SystemPerl-1.336-1.fc15.i686
| |
| | |
| perl-Verilog-CodeGen-0.9.4-5.fc15.noarch
| |
| | |
| perl-Verilog-Readmem-0.04-5.fc15.noarch
| |
| | |
| | |
| [[Category:Docs Project]] | | [[Category:Docs Project]] |
| [[Category:Draft documentation]] | | [[Category:Draft documentation]] |
| [[Category:Documentation beats]] | | [[Category:Documentation beats]] |
