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= Fedora Electronic Laboratory =
#REDIRECT [[Electronic Lab]]
 
== Website and Downloads ==
 
Fedora Electronic Lab's website is now hosted on [http://chitlesh.fedorapeople.org/FEL/ http://chitlesh.fedorapeople.org/FEL/] . It entails more details.
 
{{Admon/caution | [http://chitlesh.fedorapeople.org/FEL/fel-flyer8.pdf Fedora Electronic Lab Flyer]}}
 
{{Admon/caution | [http://torrent.fedoraproject.org/torrents//Fedora-8-Live-FEL-i686.torrent FEL 8 Livecd]  (This is a torrent file which can be used with azureus or ktorrent)}}
 
== Summary ==
 
"Fedora Electronic Lab" is yet again a Feature for Fedora 10.
 
For Fedora 10's release, "Fedora Electronic Lab" still targets mainly the Micro-Nano Electronic Engineering field. A lot of effort is being made to spin out a LiveDVD based on Fedora KDE4 livecd.
 
It introduces
* tools for '''A'''pplication-'''S'''pecific '''I'''ntegrated '''C'''ircuit ('''ASIC''') '''Design Flow''' process to the Fedora Collection for ASIC Design Flow (both for Front End and Back End design).
* extra open source standard cell libraries supporting a feature size of 0.13µm
* extracted spice decks which are simulated with gnucap/ngspice
* more interoperability between CAD tools.
 
It is intended for electronic, '''VLSI''' ('''V'''ery '''L'''arge '''S'''cale '''I'''ntegration) students and hobbyists for educational purposes.
 
== Owner ==
* Name: ChitleshGoorah
== Benefit to Fedora ==
 
Fedora is the first Linux distribution which considers to ship and provide adequate opensource tools to VLSI users and to more than 250 universities around the world.
 
Ultimately, tagging "Micro Nano Electronic CADs at the Fedora Project".
 
Interoperability between opensource Layout Editors and between Hardware Language Descriptions sustains the living Fedora culture to meet Interoperability as much as possible.
 
{{ Admon/tip | Fedora Electronic Lab needs to be included in '''F10's release notes'''.}}
 
Even if the targeted public might be a niche target user, if a university lab decides to switch to fedora to use the lab, there might more than 20 computers running fedora afterwards :) Let's take over the niche :-D
 
{{ Admon/tip | On 2008-01-18 FEL LiveCD shipped with YOU Magazine in ASIA }}
RahulSundaram and MirjamWaeckerlin [https://www.redhat.com/archives/fedora-marketing-list/2008-January/msg00154.html pointed] to You magazine [http://www.efymag.com/currentissue.asp?id=12 current] issue bundles Fedora Electronic Lab Live CD. This print magazine claims to be the only Asian print magazine dedicated to Linux and has tens of thousands of copies circulation rate. Since they also run a sister magazine called Electronics For You, they have a good interest in electronics which probably explains the choice.
 
== User Experience ==
 
* A complete VLSI Simulation Kit Electronic Engineering ensuring Interoperability.
* Interoperability between Hardware Description Languages
* Interoperability between opensource Layout Editors which Fedora is shipping :
  * alliance
  * magic
  * toped
* Field of expertise provided are mentioned in [wiki:Features/FedoraElectronicLab#details Detail Descriptions] :
* extra open source standard cell libraries at disposal (Feature Size: 0.13µm) for Alliance and magic
 
Among all these, Fedora users benefit (for free) the experience of a EDA/CAD team who has working knowledge in the ASIC industry. This EDA/CAD team works closely with upstream to provide Fedora users the latest updates and enhancements brought forward.
 
== FAQ ==
* How can I install all the gEDA/gaf applications at once ?
  # yum install geda\*
* What are the backends supported by gnetlist (from geda-gnetlist?
  $ gnetlist -g help<BR>will list all the available backends of gnetlist.
* The VHDL backend of gnetlist can't be trusted when I extract the VHDL netlists from the schematics drawn by gschem.
  Real logic designs are captured as Verilog or VHDL in text format, and compiled directly to programming files
  which are loaded into FPGAs, CPLDs, and the like. At the schematic level one just draws lots of boxes with lots of
  pins corresponding to the FPGA or CPLD. Therefore, using gschem to draw a logic circuit and then netlist to
VHDL isn't a commonly used design flow nowadays. Instead, people just create a textual design using a text editor.
* Where can I get more standard cell libraries ?
  Fedora provides standard cell libraries (sclib, wsclib, vxlib, vgalib and rgalib) from [http://www.vlsitechnology.org/ vlsitechnology.org]
  (LGPL thanks to Graham Petley)
    * yum install pharosc\*
    * [http://mosis.org mosis.org]
    * From your educational institutions
    * From other vendors depending on your use
* What can't Fedora ship more Open source standard cell libraries ?
  We have been in contact with [http://www.vlsitechnology.org/ Graham Petley]  (author of vsclib, wsclib, vxlib, vgalib and rgalib shipped with
  pharosc). We are working with him to make pharosc more distribution independent and to provide testing grounds.
  Right now, fedora users can yum install pharosc with "yum install pharosc\*"
* I want to donate my standard cell libraries to the Fedora Project, what should I do ?
Contact ChitleshGoorah: [[MailTo(chitlesh I DONT WANT SPAM @fedoraproject DOT org)]. He will package and include
it for Fedora.
 
== Glossary ==
 
* ASIC : Application-Specific Integrated Circuit
* gaf  : gschem and friends
* VLSI : Very Large Scale Integration, about 10⁶ to 10⁷ transistors
 
== Release Notes ==
 
With this release, the Fedora Collection entails a complete electronic laboratory setup with reliable open source design tools in order to meet one's requirements to keep one in pace with current technological race. This Electronic Laboratory can either be deployed by:
* yum or
* a custom Fedora spin
 
With packages like Alliance VLSI CAD, Magic, irsim, ngspice, ... Application-Specific Integrated Circuit (ASIC) Design Flows targeting the Micro-Nano Electronic Engineering world can be achieved and interoperability between packages are ensured.
 
The Fedora's Electronic Laboratory includes design tools for
* Analog/Digital Simulation
* Circuit Simulations
* Hardware Development (VHDL,Verilog)- Modeling, Designing, Simulation, Synthesis, Verification and Documentation
* VLSI (layout, synthesis, Finite State Machines...)
* Micro Controller (µC) Programming
* [[SIGs/Embedded|  Embedded Systems Development]]
 
This laboratory is intended for electronic, VLSI (Very Large Scale Integration, about 10⁶ to 10⁷ transistors) students and hobbyists for educational purposes.
 
 
== Packages ==
{|
|-
! colspan="4" | Packages
|-
!  Expertise || colspan="3" | Tools
|-
| Circuit Simulations || gnucap ||  [http://ngspice.sourceforge.net/ ngspice]  || [http://qucs.sourceforge.net/ qucs]
|-
| Layout Editing || [http://www-asim.lip6.fr/recherche/alliance/ Alliance VLSI CAD System]  || [http://opencircuitdesign.com/magic/index.html Magic]  || [http://www.toped.org.uk/ toped]
|-
| LVS/DRC || [http://opencircuitdesign.com/netgen/index.html netgen]  || [http://opencircuitdesign.com/magic/index.html Magic]  || [http://www-asim.lip6.fr/recherche/alliance/ Alliance VLSI CAD System]
|-
| Analog || gEDA (pcb & gerbv as well) || [http://www.lis.inpg.fr/realise_au_lis/kicad/ kicad] ||
|-
| Schematics || [http://opencircuitdesign.com/xcircuit Xcircuit]  || geda-gschem || gspiceui
|-
| Viewers || [http://www.atchoo.org/gds2pov/ gds2pov]  || drawtiming ||
|-
| Hardware Design || [http://ghdl.free.fr/ ghdl]  || freehdl ||[http://www.icarus.com/eda/verilog/index.html Icarus Verilog]
|-
| Finite State Machines || [http://www-asim.lip6.fr/recherche/alliance/ Alliance VLSI CAD System] || ||
|-
| Standard Cells || pharosc || sk2py ||
|-
| Digital|| [http://opencircuitdesign.com/irsim IRSIM] ||  ||
|-
! Other Expertise of the Lab || colspan="3" | Tools
|-
|Micro Controller (µC) Programming|| [http://gpsim.sourceforge.net/gpsim.html gpsim]  ||  [http://www.ktechlab.org/ ktechlab]  || [http://piklab.sourceforge.net/ piklab]
|-
|Embedded Systems|| [http://sdcc.sourceforge.net/ sdcc]  || Atmel AVR ||
|}
 
[[Category:ApprovedFedora8]][[Category:ProposedFedora10]]

Latest revision as of 15:17, 15 June 2010

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