From Fedora Project Wiki
(Website and Downloads: - Added mailing list info)
(init)
Line 1: Line 1:
= Fedora Electronic Laboratory =
+
'''
 +
Work is in progress to write a feature request for FEL'''
  
== Website and Downloads ==
 
  
Fedora Electronic Lab's website is now hosted on [http://chitlesh.fedorapeople.org/FEL/ http://chitlesh.fedorapeople.org/FEL/] . It entails more details. Also feel free to join the discussions on our [https://www.redhat.com/mailman/listinfo/fedora-electronic-lab-list mailing list]
+
= Feature Name =
  
{{ Admon/caution | [http://chitlesh.fedorapeople.org/FEL/fel-flyer8.pdf Fedora Electronic Lab Flyer]}}
+
Fedora Electronic Lab
  
{{ Admon/tip | For more information about [https://fedoraproject.org/wiki/Features/FedoraElectronicLab8 FEL 8 Livecd] }}
+
== Summary ==
 +
 
 +
This page is a feature request to FESCo with respect to the work done on the Fedora Electronic Lab. Below entails the highlights of the major development item :
 +
* Perl modules to extend vhdl and verilog support
 +
* Inclusion of the industry standard verification methodologies for ASIC design
 +
* OVM - IEEE 1800 SystemVerilog standard
 +
  * VVM - complete VMM methodology, including the VMM Standard Library, VMM Applications, utilities, macros and documentation.
 +
 
 +
== Definitions ==
  
{{ Admon/tip | FEL LiveCD was shipped with YOU Magazine in ASIA on 2008-01-18. }}
+
Below are terms used in this page which has other meanings in a normal opensource software community. These definitions are to prevent any misunderstandings from any side.
  
== Summary ==
+
* Software : a design or simulation tool that can be compiled into a RPM package
 +
* Package : Mechanical body that envelops a chip
 +
*
 +
 
 +
== Owner ==
  
"Fedora Electronic Lab" is yet again a Feature for Fedora 10.
+
* Name: [[User:chitlesh| Chitlesh Goorah]]
 +
* email: < chitlesh [AT] fedoraproject DOT org>
  
For Fedora 10's release, "Fedora Electronic Lab" still targets mainly the Micro-Nano Electronic Engineering field. A lot of effort is being made to spin out a LiveDVD based on Fedora KDE4 livecd.
+
== Current status ==
 +
* Targeted release: [[Releases/{{FedoraVersion||next}} | {{FedoraVersion|long|next}} ]]
 +
* Last updated: 19 January 2009
 +
* Percentage of completion: 60%
  
It introduces
+
== Detailed Description ==
* tools for '''A'''pplication-'''S'''pecific '''I'''ntegrated '''C'''ircuit ('''ASIC''') '''Design Flow''' process to the Fedora Collection for ASIC Design Flow (both for Front End and Back End design).
 
* extra open source standard cell libraries supporting a feature size of 0.13µm
 
* extracted spice decks which are simulated with gnucap/ngspice
 
* more interoperability between CAD tools.
 
  
It is intended for electronic, '''VLSI''' ('''V'''ery '''L'''arge '''S'''cale '''I'''ntegration) students and hobbyists for educational purposes.
+
Below entails the highlights of the major development item :
 +
* Perl modules to extend vhdl and verilog support
 +
* Inclusion of the industry standard verification methodologies for ASIC design
 +
  * OVM - IEEE 1800 SystemVerilog standard
 +
  * VVM - complete VMM methodology, including the VMM Standard Library, VMM Applications, utilities, macros and documentation.
 +
* Introduction of Verilog-AMS modeling into ngspice
 +
* Improved support for re-usable HDL packages as IP core
 +
* Improved PLI support on both iverilog and ghdl
 +
* Introduction of SystemVerilog and Synthesis assertions into C++ or SystemC code for Verilog
  
== Owner ==
 
* Name: ChitleshGoorah
 
 
== Benefit to Fedora ==
 
== Benefit to Fedora ==
  
Fedora is the first Linux distribution which considers to ship and provide adequate opensource tools to VLSI users and to more than 250 universities around the world.
+
Fedora benefits from FEL in various ways as FEL extends Fedora's commitment for opensource content in the hardware design community.
  
Ultimately, tagging "Micro Nano Electronic CADs at the Fedora Project".
+
The Fedora Project during the last 3 Fedora releases has established its roots deep into the opensource EDA community as a robust and successful opensource EDA provider.
  
Interoperability between opensource Layout Editors and between Hardware Language Descriptions sustains the living Fedora culture to meet Interoperability as much as possible.
+
FEL is not a --package-only-EDA-tools-- community, but a clear goal to strengthen the opensource EDA community, in terms of marketing, methodologies, design flows,..
  
Even if the targeted public might be a niche target user, if a university lab decides to switch to fedora to use the lab, there might more than 20 computers running fedora afterwards :) Let's take over the niche :-D
+
== Scope ==
  
{{ Admon/tip | On 2008-01-18 FEL LiveCD shipped with YOU Magazine in ASIA }}
+
FEL  
RahulSundaram and MirjamWaeckerlin [https://www.redhat.com/archives/fedora-marketing-list/2008-January/msg00154.html pointed] to You magazine [http://www.efymag.com/currentissue.asp?id=12 current] issue bundles Fedora Electronic Lab Live CD. This print magazine claims to be the only Asian print magazine dedicated to Linux and has tens of thousands of copies circulation rate. Since they also run a sister magazine called Electronics For You, they have a good interest in electronics which probably explains the choice.
 
  
{{ Admon/tip | FEL at Binghamton University}}
+
== How To Test ==
Universities like the [http://clunixchit.blogspot.com/2008/05/fedora-electronic-lab-at-binghamton.html Binghamton university] are deploying nodes with FEL installed.
+
<!-- This does not need to be a full-fledged document.  Describe the dimensions of tests that this feature is expected to pass when it is done.  If it needs to be tested with different hardware or software configurations, indicate them.  The more specific you can be, the better the community testing can be.
 +
 
 +
Remember that you are writing this how to for interested testers to use to check out your feature - documenting what you do for testing is OK, but it's much better to document what *I* can do to test your feature.
 +
 
 +
A good "how to test" should answer these four questions:
 +
 
 +
0. What special hardware / data / etc. is needed (if any)?
 +
1. How do I prepare my system to test this feature? What packages
 +
need to be installed, config files edited, etc.?
 +
2. What specific actions do I perform to check that the feature is
 +
working like it's supposed to?
 +
3. What are the expected results of those actions?
 +
 
 +
-->
  
 
== User Experience ==
 
== User Experience ==
 +
<!-- If this feature is noticeable by its target audience, how will their experiences change as a result?  Describe what they will see or notice. -->
  
* A complete VLSI Simulation Kit Electronic Engineering ensuring Interoperability.
+
== Dependencies ==
* Interoperability between Hardware Description Languages
+
<!-- What other packages (RPMs) depend on this package?  Are there changes outside the developers' control on which completion of this feature depends?  In other words, completion of another feature owned by someone else and might cause you to not be able to finish on time or that you would need to coordinate?  Other upstream projects like the kernel (if this is not a kernel feature)? -->
* Interoperability between opensource Layout Editors which Fedora is shipping :
 
  * alliance
 
  * magic
 
  * toped
 
* extra open source standard cell libraries at disposal (Feature Size: 0.13µm) for Alliance and magic
 
  
Among all these, Fedora users benefit (for free) the experience of a EDA/CAD team who has working knowledge in the ASIC industry. This EDA/CAD team works closely with upstream to provide Fedora users the latest updates and enhancements brought forward.
+
== Contingency Plan ==
 +
<!-- If you cannot complete your feature by the final development freeze, what is the backup plan?  This might be as simple as "None necessary, revert to previous release behaviour."  Or it might not.  If you feature is not completed in time we want to assure others that other parts of Fedora will not be in jeopardy. -->
  
== FAQ ==
+
== Documentation ==
*  '''Why FEL is not shipping SystemC ?'''
+
<!-- Is there upstream documentation on this feature, or notes you have written yourself? Link to that material here so other interested developers can get involved. -->
There was an attempt to include SystemC. However due to a [http://clunixchit.blogspot.com/2008/07/fel-systemc-was-put-aside-legal.html legal issue], it was put aside.
 
* '''How can I install all the gEDA/gaf applications at once ?'''
 
<pre># yum install geda\*</pre>
 
* '''What are the backends supported by gnetlist (from geda-gnetlist?'''
 
The below command will list all the available backends of gnetlist.
 
<pre>$ gnetlist -g help</pre>
 
* '''The VHDL backend of gnetlist can't be trusted when I extract the VHDL netlists from the schematics drawn by gschem.'''
 
Real logic designs are captured as Verilog or VHDL in text format, and compiled directly to programming files which are loaded into FPGAs, CPLDs, and the like. At the schematic level one just draws lots of boxes with lots of pins corresponding to the FPGA or CPLD. Therefore, using gschem to draw a logic circuit and then netlist to VHDL isn't a commonly used design flow nowadays. Instead, people just create a textual design using a text editor.
 
* '''Where can I get more standard cell libraries ?'''
 
Fedora provides standard cell libraries (sclib, wsclib, vxlib, vgalib and rgalib) from [http://www.vlsitechnology.org/ vlsitechnology.org] (LGPL thanks to Graham Petley)
 
    * yum install pharosc\*
 
    * [http://mosis.org mosis.org]
 
    * From your educational institutions
 
    * From other vendors depending on your use
 
* '''What can't Fedora ship more Open source standard cell libraries ?'''
 
We have been in contact with [http://www.vlsitechnology.org/ Graham Petley]  (author of vsclib, wsclib, vxlib, vgalib and rgalib shipped with pharosc). We are working with him to make pharosc more distribution independent and to provide testing grounds. Right now, fedora users can install pharosc with the below command.
 
<pre>#yum install pharosc\*</pre>
 
* '''I want to donate my standard cell libraries to the Fedora Project, what should I do ?'''
 
Contact ChitleshGoorah: [[MailTo(chitlesh I DONT WANT SPAM @fedoraproject DOT org)]. He will package and include it for Fedora.
 
  
== Glossary ==
 
 
* ASIC : Application-Specific Integrated Circuit
 
* gaf  : gschem and friends
 
* VLSI : Very Large Scale Integration, about 10⁶ to 10⁷ transistors
 
  
 
== Release Notes ==
 
== Release Notes ==
  
With this release, the Fedora Collection entails a complete electronic laboratory setup with reliable open source design tools in order to meet one's requirements to keep one in pace with current technological race. This Electronic Laboratory can either be deployed by:
+
<!-- The Fedora Release Notes inform end-users about what is new in the release. Examples of past release notes are here: http://docs.fedoraproject.org/release-notes/ -->
* yum or
+
<!-- The release notes also help users know how to deal with platform changes such as ABIs/APIs, configuration or data file formats, or upgrade concerns.  If there are any such changes involved in this feature, indicate them here. You can also link to upstream documentation if it satisfies this need. This information forms the basis of the release notes edited by the documentation team and shipped with the release. -->
* a custom Fedora spin
 
 
 
With packages like Alliance VLSI CAD, Magic, irsim, ngspice, ... Application-Specific Integrated Circuit (ASIC) Design Flows targeting the Micro-Nano Electronic Engineering world can be achieved and interoperability between packages are ensured.
 
  
The Fedora's Electronic Laboratory includes design tools for
+
== Comments and Discussion ==
* Analog/Digital Simulation
 
* Circuit Simulations
 
* Hardware Development (VHDL,Verilog)- Modeling, Designing, Simulation, Synthesis, Verification and Documentation
 
* VLSI (layout, synthesis, Finite State Machines...)
 
* Micro Controller (µC) Programming
 
* [[SIGs/Embedded|  Embedded Systems Development]]
 
  
This laboratory is intended for electronic, VLSI (Very Large Scale Integration, about 10⁶ to 10⁷ transistors) students and hobbyists for educational purposes.
+
* See [[Talk:Features/YourFeatureName]]  <!-- This adds a link to the "discussion" tab associated with your page. This provides the ability to have ongoing comments or conversation without bogging down the main feature page -->
  
  
== Packages ==
+
----
{|
 
|-
 
! colspan="4" | Packages
 
|-
 
!  Expertise || colspan="3" | Tools
 
|-
 
| Circuit Simulations || gnucap ||  [http://ngspice.sourceforge.net/ ngspice]  || [http://qucs.sourceforge.net/ qucs]
 
|-
 
| Layout Editing || [http://www-asim.lip6.fr/recherche/alliance/ Alliance VLSI CAD System]  || [http://opencircuitdesign.com/magic/index.html Magic]  || [http://www.toped.org.uk/ toped]
 
|-
 
| LVS/DRC || [http://opencircuitdesign.com/netgen/index.html netgen]  || [http://opencircuitdesign.com/magic/index.html Magic]  || [http://www-asim.lip6.fr/recherche/alliance/ Alliance VLSI CAD System]
 
|-
 
| Analog || gEDA (pcb & gerbv as well) || [http://www.lis.inpg.fr/realise_au_lis/kicad/ kicad] ||
 
|-
 
| Schematics || [http://opencircuitdesign.com/xcircuit Xcircuit]  || geda-gschem || gspiceui
 
|-
 
| Viewers || [http://www.atchoo.org/gds2pov/ gds2pov]  || drawtiming ||
 
|-
 
| Hardware Design || [http://ghdl.free.fr/ ghdl]  || freehdl ||[http://www.icarus.com/eda/verilog/index.html Icarus Verilog]
 
|-
 
| Finite State Machines || [http://www-asim.lip6.fr/recherche/alliance/ Alliance VLSI CAD System] || ||
 
|-
 
| Standard Cells || pharosc || sk2py ||
 
|-
 
| Digital|| [http://opencircuitdesign.com/irsim IRSIM] ||  ||
 
|-
 
! Other Expertise of the Lab || colspan="3" | Tools
 
|-
 
|Micro Controller (µC) Programming|| [http://gpsim.sourceforge.net/gpsim.html gpsim]  ||  [http://www.ktechlab.org/ ktechlab]  || [http://piklab.sourceforge.net/ piklab]
 
|-
 
|Embedded Systems|| [http://sdcc.sourceforge.net/ sdcc]  || Atmel AVR ||
 
|}
 
  
[[Category:ApprovedFedora8]]
+
[[Category:FeaturePageIncomplete]]
 +
<!-- When your feature page is completed and ready for review -->
 +
<!-- remove Category:FeaturePageIncomplete and change it to Category:FeatureReadyForWrangler -->
 +
<!-- After review, the feature wrangler will move your page to Category:FeatureReadyForFesco... if it still needs more work it will move back to Category:FeaturePageIncomplete-->
 +
<!-- A pretty picture of the page category usage is at: https://fedoraproject.org/wiki/Features/Policy/Process -->

Revision as of 22:22, 19 January 2009

Work is in progress to write a feature request for FEL


Feature Name

Fedora Electronic Lab

Summary

This page is a feature request to FESCo with respect to the work done on the Fedora Electronic Lab. Below entails the highlights of the major development item :

  • Perl modules to extend vhdl and verilog support
  • Inclusion of the industry standard verification methodologies for ASIC design
* OVM - IEEE 1800 SystemVerilog standard
* VVM - complete VMM methodology, including the VMM Standard Library, VMM Applications, utilities, macros and documentation.

Definitions

Below are terms used in this page which has other meanings in a normal opensource software community. These definitions are to prevent any misunderstandings from any side.

  • Software : a design or simulation tool that can be compiled into a RPM package
  • Package : Mechanical body that envelops a chip

Owner

Current status

  • Targeted release: Fedora 31
  • Last updated: 19 January 2009
  • Percentage of completion: 60%

Detailed Description

Below entails the highlights of the major development item :

  • Perl modules to extend vhdl and verilog support
  • Inclusion of the industry standard verification methodologies for ASIC design
 * OVM - IEEE 1800 SystemVerilog standard
 * VVM - complete VMM methodology, including the VMM Standard Library, VMM Applications, utilities, macros and documentation.
  • Introduction of Verilog-AMS modeling into ngspice
  • Improved support for re-usable HDL packages as IP core
  • Improved PLI support on both iverilog and ghdl
  • Introduction of SystemVerilog and Synthesis assertions into C++ or SystemC code for Verilog

Benefit to Fedora

Fedora benefits from FEL in various ways as FEL extends Fedora's commitment for opensource content in the hardware design community.

The Fedora Project during the last 3 Fedora releases has established its roots deep into the opensource EDA community as a robust and successful opensource EDA provider.

FEL is not a --package-only-EDA-tools-- community, but a clear goal to strengthen the opensource EDA community, in terms of marketing, methodologies, design flows,..

Scope

FEL

How To Test

User Experience

Dependencies

Contingency Plan

Documentation

Release Notes

Comments and Discussion